The Complete Verilog Book

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The book is written with the approach that Verilog is not only a simulation or synthesis language, or a formal method of describing design, but a complete language addressing all of these aspects. This book covers many aspects of Verilog HDL that are essential parts of any design process. Read more Read less. Customers who viewed this item also viewed.

Page 1 of 1 Start over Page 1 of 1. Verilog HDL 2nd Edition. Springer; Softcover reprint of the original 1st ed. Related Video Shorts 0 Upload your video. Try the Kindle edition and experience these great reading features: Share your thoughts with other customers. Write a customer review. There was a problem filtering reviews right now.

Please try again later. This book is really a worthwhile book to read and study for advanced topics of designs based on Verilog and Synopsys synthesis tools. The feature-rich topics and details of how the constructs of the designs are made are quite clear and well-written for people involved. Amazon Giveaway allows you to run promotional giveaways in order to create buzz, reward your audience, and attract new followers and customers.

Learn more about Amazon Giveaway. The Verilog hardware description language provides the ability to describe digital and analog systems for design concepts and implementation. It was developed originally at Gateway Design and implemented there. The Complete Verilog Book introduces the language and describes it in a comprehensive manner. These can be constants, parameters, expressions of these or even dynamic expressions using other variables.

Delays can be rise, fall, or hold change to z delays and each of these delays in turn may have three values—minimum, typical and maximum. The rise, fall and hold delay specifications are separated by commas and the min-typ-max specifications are separated by colons. The rise delay includes delays when values change from 0 to 1, 0 to x and x to 1.

Fall delay applies to changes from 1 to 0, 1 to x and x to 0. The hold delay values apply for changes from 0 to z, 1 to z and x to z changes. The same concepts of delays are useful for gates, transistors, user-defined primitive instances and behavioral descriptions. Net declarations with delay specifications.

In the first example above, t1 and t2 have rise, fall and hold delays of five time units. In the second line, wires w1 and w2 have three different values for the three changes—ten for rise, nine for fall, and eight for hold. The rise delay includes delays when values change from 0 to 1,0 to x and x to 1. The type integer is 32 bit and can be assigned and used freely as integer or bit signed register in expressions, 2. Integer and time declarations. Their bit representation is done using IEEE floating point standard. Example and syntax are: However, the Verilog language requires that you define the parameter before you use it.

Example shows two parameter declarations. Parameters SO, S1, S2, and S3 have values 3, 1, 0, and 2, respectively, and are stored as 2-bit quantities. Parameters are a way of defining modules which can be configured at the instance time. The module instantitation statement lets one change the values of parameters in a module to new values for each instance. This facility is extensively used for operations such as delay back-annotations from a post-layout circuit into a pre-layout or rtl design.

These expressions may be of any valid data-type, like bits, vectors, integer, or reals in Verilog. These are full hierarchical names as follows: Typically these are used in back-annotations or forward-annotations from outside the current design description. SDF files described in chapter 18, may, for example, be used to generate delay files using full-hierarchical names. These are also very useful for debugging as seen in Chapter The usage of these for circuit description should be done with discretion since one is creating connections across module boundaries without putting the connecting wires or regs on the port list.

The name begins with a top-level module-name testbench and then is followed by instance names until the level at which the name is defined is reached. Write a declaration for a wire and bus of 64 bits wide and a rise delay of 10 and fall delay of 8 time units. Write memory declarations for a 64K x 8-bit memory. Check the correctness of the following declarations: Write a declaration of a tri-state wire with charge storage of medium capacitance.

In Example , change the net-type to triand and trior and trireg from tri and then compute the expected results. Three commonly understood levels of abstraction are behavioral, register-transfer-level RTL , and structural.

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The three types of descriptions together constitute the descriptions of hardware in a hardware description language. These are explained in the following sections of this chapter. In the above example, a multiplier is modeled at the behavioral and at the RTL level. For descriptions like these, both behavioral and RTL models are used. The behavioral model always uses blocks with procedural statements, while the RTL model uses continuous assignments that begin with keyword 'assign'.

This enables descriptions that are algorithmic descriptions of hardware.

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It enables synchronization between different blocks or processes. This is the highest level of abstraction among the three levels including the structural and the RTL. Control flow modeling in Verilog at this level is substantially improved. Verilog derives some of the basic algorithm description capabilities from structured programming aspects of "C", but with specific facilitations for hardware descriptions.

Synchronization or timing controls features are also quite advanced especially when mixed with the copious control flow capabilities. The whole design is represented as concurrently executing processes or evaluation blocks as explained in Chapter 4. Specially created timing specification blocks Specify Blocks provide rich intermodule timing behavior description in Verilog. This is structurally bound to the module pins or inputs-outputs. Use of operator b.

Use of vectorizing c. Behavioral level of abstraction — adder. In the above example, adder is modeled behaviorally using always loop. The addition operation, using 2 bits with the tmp[1: The next two statements separate out the 2 bits into the sum and cOut bits that appear on the module boundary.


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Data transfer between registers is known as RTL transfer and the event-driven model as basis for these transfers. The event-driven model here is crucial to these descriptions. In Verilog, the mechanism to model these is called continuous assignments. This will be the main driver in logic synthesis, especially for datapath.

Control Logic comes from FSM descriptions that will be discussed later. Thus, there is no order implied by the model in these. However, due to the event driven nature of these and the fact that these are interdependent, will create an order like in the hardware that is being modeled. As the RTL descriptions are in between structural and behavioral, these work in between the other two. In these, we drive the left-hand side just like in ports that are input ports, the rules for ports that can be driven apply here.

Thus, we will only use types that are physically realizable or can physically be driven on a continuous basis. Registers reg declarations are one-shot deals as far as assignments are concerned. They are assigned when we get to them in a serial block in "C"-like fashion. But the continuous assigns can only happen on nets. In Verilog, one is allowed to use concatenations of nets as a vector net with no name like in a synthesizer with property on the net, to keep it post-synthesis.

This is useful at times, but it is better to create another net and assign the concatenations all other nets to this net. This helps in debugging and better readability of the code. Like "C", one can also combine the declaration and assignment for nets with continuous assignments. This is the first abstraction from a gate-level description. Rather than use an and gate, one would write: Boolean Algebra is also now applicable for optimizations and reorganizations. The additional modeling capabilities here include: See the examples below and syntax as well for details. If you want to drive a value onto a wire, wand, wor, or tri, use a continuous assignment to specify an expression for the wire's value.

You can specify a continuous assignment in two ways: Use an explicit continuous assignment statement after the wire, wand, wor, or tri declaration. Specify the continuous assignment in the same line as the declaration for a wire. Example shows two equivalent methods for specifying a continuous assignment for wire a. Two equivalent continuous assignments. RTL abstractions — adder.

RTL abstractions — adder with boolean optimizations. Continuous assignments — RTL modeling. This typically includes state descriptions using behavioral blocks, and combinational description using behavorial or continuous assignments. Expressions provide ability to abstract operations up from the gate-level. Expressions consist of operators and operands. The operands are formed by the various data declared items like nets, regs, integers, reals, time, event, etc. They may also be formed by sub-expressions which may be parenthesized. The operators are formed by symbols that represent operations such as addition, subtraction, multiplication, etc.

Most operators are either unary operators that apply to only one operand, or 44 Chapter 3 binary operators that apply to two operands. Two exceptions are conditional operators, which take three operands, and concatenation operators, which take any number of operands.

Verilog provides a rich set of operators as described in the next few pages. The main operators under various categories are: This group includes wires and registers, bit-selects, and part-selects of wires and registers, function calls, and expressions that contains any of these elements. The Verilog arithmetic operators are: Example shows three forms of the addition operator. Relational Operators Relational operators compare two quantities and yield a 0 or 1 value. A true comparison evaluates to 1; a false comparison evaluates to 0. All comparisons assume unsigned quantities.

The Verilog relational operators are: Equality and inequality comparisons are performed bit-wise. The Verilog equality operators are: The output signal opcode is set to 1 if the two high-order bits of instruction are equal to the value of parameter JMP; otherwise jump is set to 0. Logical Operators Logical operators generate a 1 or a 0, according to whether an expression evaluates to true 1 or false 0. The Verilog logical operators are: The logical and operator produces a value of 1 if both operands are nonzero. The logical or operator produces a value of 1 if either operand is nonzero.

Example shows some logical operators. The Verilog bit-wise operators are: Reduction Operators Reduction operators take one operand and return a single bit. For example, the reduction and operator takes the and value of all the bits of the operand and returns a 1-bit result. After the shift, vacated bits are filled with zeros. Example shows how a right-shift operator is used to perform a division by 4. If Operators If or Conditional operators? Example shows how to use conditional operators. Conditional operators can be nested to produce an if. Example shows the conditional operators?

Concatenations Concatenation combines one or more expressions to form a larger vector. Any expression except an unsized constant is allowed in a concatenation.

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You can also use a constant-valued repetition multiplier to repeat the concatenation of an expression. Example shows a concatenation that forms the value of a condition-code register. Example shows an equivalent description for the concatenation. Numbers Wires and registers Bit-selects Part-selects Function calls Integers Reals Time Thus, any data type declared using statements discussed in Chapter 2 and its derivative can be used in an expression.

The following pages discuss the usage of various types of operands in an expression. You can define constants as sized or unsized, in binary, octal, decimal, or hexadecimal bases. The default size of an unsized constant is 32 bits. Size is written as a decimal number like 32 or Different representations of constant 10 in Verilog. Wires and Registers Variables that represent both wires and registers are allowed in an expression. If the variable is a multi-bit vector and you use only the name of the variable, the entire vector is used in the expression. Bit-selects and part-selects allow you to select single or multiple bits, respectively, from a vector.

These are described in the next two sections. In the Verilog fragment shown in Example , a, b, and c are 8-bit vectors of wires. Since only the variable names appear in the expression, the entire vector of each wire is used in evaluating the expression. Bit-Selects A bit-select is the selection of a single bit from a wire, register, or parameter vector.

The value of the expression in brackets [ ] selects the bit you want from the vector. The selected bit must be within the declared range of the vector. Example shows a simple example of a bit-select with an expression. Part-Selects A part-select is the selection of a group of bits from a wire, register, or parameter vector. The part-select expression must be constant-valued in the Verilog language, unlike the bit-select operator.

If a variable is declared with ascending indices or descending indices, the part-select when applied to that variable must be in the same order. The expression in Example can also be written with descending indices as shown in Example Function Calls Verilog allows you to call one function from inside an expression and use the return value from the called function as an operand. Functions in Verilog return a value consisting of one or more bits. The syntax of a function call is the function name followed by a comma-separated list of function inputs enclosed in parentheses.

Example shows the function call fcall used in an expression. Function call used as an operand. Functions are described in detail in Chapter 5 on Behavioral Descriptions Concatenation of Operands Concatenation is the process of combining several single- or multiple-bit operands into one large bit vector. Example shows two bit vectors halfword1 and halfword2 that are joined to form a bit vector that is assigned to a bit wire vector byte.

Integers and Time Integers and time are bit and bit quantities respectively and can be used as such. All the operations on vector-regs can then be used on these types of operands. Reals Reals can be used in expressions to evaluate different arithmetic operations. If the value of op is 1, b is added to a; otherwise, b is subtracted from a. In general, the bit representation for reals is not considered unique, and thus, bit-operations on these are not defined. Examples of operator usage. Thus, in the following example, the three assignments to c all perform bit arithmetic.

In earlier versions of Verilog, the first assignment to c would result in bit operation and potential loss of carry. Different ways to perform sized operations. Datapath design using continuous assignments RTL abstractions. Modules in turn can have other modules, behavioral blocks, RTL descriptions, built-in gates and transistors single bits , and user-defined primitives.

The other modules are included using the constructs of module instantiations. The gates, switches and udps can be viewed as predefined modules. Then rules for instancing these fall into the rules of instancing modules. Structural design — A CPU with details of adder at the gatelevel. These form a basic design unit that can be instantiated.

Module allows creating different views of the same design unit [architectural, rtl, structural]. Each module has its own namespace or scope. It also has IOs, parameters and body. The transfer of data across a module boundary happens via well-defined interface known as the ports of a module. These have been defined in the section 2. The syntax section 3. A body of a module has everything else in the language, i. A module has data declaration of type parameters. Parameters are a way of defining generic units that can be configured in some dimensions at instance time or at redefinition.

Verilog parameters allow you to customize each instantiation of a module. By setting different values for the parameter when you instantiate the module, you can cause different logic to be constructed. Back-annotating delays is the most common application of parameters. A parameter represents constant values symbolically. The definition for a parameter consists of the parameter name and the value assigned to it. The value can be any constant-valued expression of integer or Boolean type, but not of type real.

If you do not set the size of the parameter with a range definition or a sized constant, the parameter is unsized and defaults to a bit quantity. Example of parametrized module definitions. Parameters Verilog parameters allow you to customize each instantiation of a module. The typical uses of parameters are in delays and sizes, but they have broad applications. Macromodules Macromodules allow definition of modules that get compiled as parts of the modules in all instantiations without the module boundaries.

Example of a macromodule construct. Named Ports in Modules module ex4. Named ports in modules. You can rename a port by explicitly assigning a name to a port expression by using the dot.


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The module definition fragments in Example show how to rename ports. Module ex5 shows ports named il, i0, and z connected to nets a[l], a[0], and z, respectively. The first port for module ex6 the concatenation of nets a and b is named i. It is also a mechanism to describe connectivity and a mechanism to create hierarchical design.

This is a mechanism to select various views of the design units. This supports hierarchical names. Module instantiations are copies of the logic in a module that define component interconnections. A module instantiation is done using the following form: A connection list is a list of expressions called terminals, separated by commas.

These terminals are connected to the ports of the instantiated module. Terminals connected to input ports can be any arbitrary expression. Terminals connected to output and inout ports can be identifiers, singleor multiple-bit slices of an array, or a concatenation of these. The bit widths for a terminal and its module port must be the same. Named and Positional Notation Module instantiations can use either named or positional notation to specify the terminal connections. In name-based module instantiation, you explicitly designate which port is connected to each terminal in the list.

Undesignated ports in the module are unconnected. In position-based module instantiation, you list the terminals and specify connections to the module according to the terminal's position in the list. The first terminal in the connection list is connected to the first module port, the second terminal to the second module port, and so on.

Omitted terminals indicate that the corresponding port on the module is unconnected. If you use an undeclared variable as a terminal, the terminal is implicitly declared as a scalar 1-bit wire. After the variable is implicitly declared as a wire, it can appear wherever a wire is allowed 3. Bus0 i2 ; endmodule Example Signal D3 is connected to port BUS1. Signal D2 is connected to port BUS0. Signal Dl is connected to port BUS1. Module definitions and instantiation — hierarchical design example.

A structural model of R processor with declarations and instances at top-level Example 3 In this example, we describe the input-outputs and top-level units of ultrasparcIIi. Figure on page 82 depicts the block diagram. A single-chip implementation, UltraSparc Iii integrates the following components: Instantiate the two modules in Example in a test module. Apply stimulus and see the two modules give out exactly the same results. Use the Example as a guideline to writing this test module. Convert the following RTL description into a behavioral statement using case statement.

Given that a, b and c are declared as below: The barrel shifter in the Example shifts or rotates by 1 bit. Modify the barrel shifter to have a module port that contains the number of bits to be shifted. Port declarations will also be added for the new port]. Create a testbench for this, test and obtain results. This specification can then be used for verification by a simulator, by a formal verification tool, or for synthesis or timing analysis or any other process pertaining to the design. The syntax of the language is defined precisely by a formal notation like BNF. However, the semantics definition of a language does not have a formal notation developed and usable in the realm of computer science.

Thus, to help understand the commonly understood semantics of a program in a language, some abstract models are used. Here a model is provided based on the original ideas that we had while designing and implementing the language. This model is based on the notion of value-changes and evaluations and their sequencing.

The simulation can be thought of a series of value-changes on signals nets and regs intermixed with evaluations of blocks of Verilog Code that describe circuit elements. The Verilog model is given below: In this example, behavioral representation is used for stimulus and result capturing, while gates are used to describe the design. The rules of semantics in a behavioral block are the same whether it is used for test bench or design description, and the explanation in the following sections will apply to examples containing behavioral description of design.

In some ways, the single stepping is stepping through the sequence of evaluations. Thus, with these two traces, we can see some series of evaluations and value-changes that makes the simulation run for a given Verilog model. Capturing this in a log file and visiting this later also gives us the insight into what is happening in the simulation cycles that lead to the whole simulation. Here we list an ideal log file while running on your favorite simulator will typically produce a subset of this information. The log file on a sample simulator is also shown for comparison.

V No errors in compilation Top-level modules: Thank you for using VeriWell for Win32 Example Log of a typical simulator with tracing.

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Ideal simulation log for a sample circuit with tracing. Simulation starts at time 0 when, the model performs evaluations of all initial and always blocks. The evaluation of a block continues this until it suspends or schedules itself for a later time. During the course of this evaluations, value changes on reg variables are effected and their fanouts are evaluated or are scheduled for evaluations.

This may or may not result in further value changes to be scheduled. This can be called the network data structure. In the above diagram, the rectangles represent the evaluation blocks and the ellipses represent the signals. The names of these are given inside and these correspond to the names in the design. Coupled with this is the event queue data structure that now enables us to see throughout this event driven simulation cycle in Verilog HDL.

This is reflected in two types of events in the event queue also known as scheduler —Update Event and Evaluate Events. In a model known as 2 pass model, the types of events are held in separate lists and are processed in two passes—the first pass for update and second for evaluate. Each initial and always block, continuous assignments, structural gates, udp instances, and transistors form parallel blocks in Verilog.

A simulator can choose an order in any manner for all events that are scheduled to happen at the same time. This happens when multiple processes update a reg at the same time with no interdependence. This results in non-determinism OR different results on different simulators or in different simulation runs on the same simulator. A simple example of non-determinism is as follows: This can be a driver on a net of any type like tri, triand etc. Process or Evaluation Block — A basic unit of evaluation in Verilog.

Verilog objects — Signals and Evaluation Blocks form basic Verilog objects which form units of activity in the Verilog model. An event has the following three attributes associated with it: The activity that defines the event can be of the following two types making the event type. Update Event — The activity indicating a value change on a signal. Evaluation Event — The activity indicating evaluation of a block process.

Schedule — List of all events in the Verilog model at any time. Network Representation of Verilog — A network consisting of Evaluation Blocks, Signals and their interconnections is a mapping from a given Verilog description. More on the effects of evaluation events. Set current time to 0.

Schedule evaluation events on all behavioral blocks for current time and update events for all UDP outputs with initial state. If block is behavioral also remove it from fanout list. For example, in a computer, CPU, memory, peripheral boards like the IO controllers floppy disk controller , hard disk controller are always running in parallel. The states of some units may imply waits but they will be providing certain outputs as a function of inputs and current state, independent of other units.

A hardware description language must model this behavior correctly. In the above algorithm, we can clearly see that all the always blocks and the initial blocks in the behavioral description of the Verilog model are executed concurrently.


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  • Similarly, the gates, module instances, UDPs and the RTL assignments are continuously providing the outputs as a function of inputs. In an event-driven model, this translates into creating an evaluation event on the evaluation blocks whenever one of the inputs changes. This again can be seen in the above algorithm. In terms of the network-data structure, all the rectangles representing the evaluation blocks are executing concurrently.

    Events may be present on one or all of them at the same time within the schedule. The following two examples illustrate the inertial delay model followed in general in Verilog and described in the algorithm above. Multiple events on a reg — but no cancellation algorithm applied Running this produces the following results: Thus, the event created at time for out to change to 1 does not get descheduled at time 3 as the new value of out is consistent with the scheduled value.

    However, in the following example, for the and gate, new value is different and the event is canceled and replaced with a new event with a different output value and different time of change. Multiple events on a reg resulting cancellation algorithm applied In this example, at time 3 units, an event gets created on out to change at 8 time units. This event gets canceled at time 5 units when in1 changes to 0.

    A new event for out to change at 10 is created to change to 0. This is generally known as inertial delay model. The transport delay model is supported in Verilog by use of non-blocking assignments as explained in the next chapter. This depends on the new value and the scheduled value. In Verilog, typically only one event can be present on a net or a reg at a time. Exceptions to these are events arising out of non-blocking assignments. This allows modeling algorithmic style descriptions.

    Naturally, we need the ability to capture the algorithms like in a programming language. This is provided with "C"-like statements—assignments, ifelse, case, for loop , begin-end blocks, functions and procedures tasks. Verilog is essentially a Concurrent Programming Language. This implies that we need a mechanism to synchronize the algorithmic descriptions together with the structural and RTL descriptions.

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    This is provided by 'initial' and 'always' blocks that enclose all algorithmic descriptions. Within each of these blocks, timing controls or synchronization primitives are provided in terms of delays, event controls, fork-join statements, and wait statements.

    The algorithmic descriptions are also called sequential blocks and the statements are termed sequential statements. This does not imply that these are sequential designs—the term originates from 'in sequence' or 'in order'. No storage is implied in these descriptions. The top level blocks are the initial and the always blocks in the behavioral descriptions. The tasks and function declarations also occur at the same top level in a module.

    In the Example , clock is generated behaviorally. One initial and one always block is used. The tasks and functions are explained in section 5. The initial and always are expanded as follows: All algorithmic descriptions can be thought of as temporary computations whose results can then be put onto physical entities like nets via RTL or gate descriptions that are closer to physical reality. Thus, the original intent of behavioral level HDL is to allow expressing your ideas into a precise form whose results can be easily transferred to the RTL and structural level for ease of development.

    This will allow stepwise refinement of your model from a higher level description into gates. All non-net constructs reg, integers, reals, time and any aggregate of these are abstract and there are different ways to actualize these into hardware. Synthesis has some role to play here, but in reality, a very small subset of the behavioral level is synthesized by logic synthesis and some larger subset by behavioral synthesis.

    Blocking assignments — inter-assignment delays In this example, the assignment to regc happens after assignments to rega and regb are complete at time 5 units. The previous assignments to rega and regb at time 0 are overridden with the assignments at time 5 before the right-hand side expression for assignment to c is computed. This implies that regc gets a value of 1 and is displayed as such at time of 10 units.

    This is in contrast with the Example where the non-blocking assignments take place in a deferred manner. The delays of 5 time units ocurring twice in this example are between the assignments and block the flow of control of this behavioral block or process for 5 time units each.

    This is in Chapter 5 contrast to intra-assignment delays explained later. There is no scheduling activity involved in the blocking assignments. Blocking Assignment — intra-assignment delays. In the above example, the delays are present inside the assignment statement which implies that they are intra-assignment delays as opposed to the interassignment delays of Example The righthand side would then be from previous state while the left-hand side will get the new value in this state.

    This kind of modeling is not possible with blocking assignments and the concept of non-blocking assignment is introduced. To allow modeling whereby a state of the system is captured at a delta cycle time and then all values are determinable by the delta cycle of the simulator, notion of non-blocking procedural assignments was introduced in later versions of Verilog. This nonblocking type of assignment is a better model for most real registers when modeling synchronous systems.

    However, by following certain consistent conventions throughout Verilog model, one can use the blocking assignments which are more efficient for simulation and which are easier to understand. In this example, the assignment to regc happens with the right-hand side computed before new assignments to rega and regb are complete at time 5 units.